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| author | Daniel P. Berrange <berrange@redhat.com> | 2012-04-13 11:39:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-04-13 11:39:06 +0000 |
| commit | b85f62d7811c80646065f8f96c2248ea86cfd911 (patch) | |
| tree | d5d36a2368e44af7933339643dee15559937baf5 | |
| parent | dadc1064c348545695b8a14d9dc72ccaa2983be7 (diff) | |
| download | focaccia-qemu-b85f62d7811c80646065f8f96c2248ea86cfd911.tar.gz focaccia-qemu-b85f62d7811c80646065f8f96c2248ea86cfd911.zip | |
Fix bit test in Exynos4210 UART emulation to use & instead of &&
* hw/exynos4210_uart.c: s/&&/&/ Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/exynos4210_uart.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c index 73a9c18f30..ccc47804f9 100644 --- a/hw/exynos4210_uart.c +++ b/hw/exynos4210_uart.c @@ -246,7 +246,7 @@ static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s) uint32_t level = 0; uint32_t reg; - reg = (s->reg[I_(UFCON)] && UFCON_Tx_FIFO_TRIGGER_LEVEL) >> + reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >> UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT; switch (s->channel) { @@ -275,9 +275,9 @@ static void exynos4210_uart_update_irq(Exynos4210UartState *s) * The Tx interrupt is always requested if the number of data in the * transmit FIFO is smaller than the trigger level. */ - if (s->reg[I_(UFCON)] && UFCON_FIFO_ENABLE) { + if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) { - uint32_t count = (s->reg[I_(UFSTAT)] && UFSTAT_Tx_FIFO_COUNT) >> + uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >> UFSTAT_Tx_FIFO_COUNT_SHIFT; if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) { |