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| author | Frank Chang <frank.chang@sifive.com> | 2021-12-10 15:56:40 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-12-20 14:53:31 +1000 |
| commit | b8dd99f2d10311e0f4527507f56a1721e9c19505 (patch) | |
| tree | de8689de415d8802c20e5eeb72fbb34dfb7ae103 | |
| parent | 08b60eebc4ac101eef94639553766c3c1969c4d3 (diff) | |
| download | focaccia-qemu-b8dd99f2d10311e0f4527507f56a1721e9c19505.tar.gz focaccia-qemu-b8dd99f2d10311e0f4527507f56a1721e9c19505.zip | |
target/riscv: rvv-1.0: widening floating-point reduction instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211210075704.23951-55-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 998247d71d..b43234ed3f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2648,7 +2648,14 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) /* Vector Widening Floating-Point Reduction Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) +static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_widen_check(s, a) && + require_scale_rvf(s) && + (s->sew != MO_8); +} + +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) /* *** Vector Mask Operations |