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| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-09-27 00:56:22 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-09-27 00:57:41 +0200 |
| commit | bedda79c1eecb62316dc7698a886262fd496864e (patch) | |
| tree | 2a63295debb79d306766ca5c497ef7605bf32b4c | |
| parent | 5b207c007c445d6a5a051a753d506bdae83d0b49 (diff) | |
| download | focaccia-qemu-bedda79c1eecb62316dc7698a886262fd496864e.tar.gz focaccia-qemu-bedda79c1eecb62316dc7698a886262fd496864e.zip | |
target-i386: kill a tmp register
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-i386/translate.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 74b4f66b64..3eae9bc643 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -69,7 +69,7 @@ static TCGv cpu_tmp0, cpu_tmp4; static TCGv_ptr cpu_ptr0, cpu_ptr1; static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32; static TCGv_i64 cpu_tmp1_i64; -static TCGv cpu_tmp5, cpu_tmp6; +static TCGv cpu_tmp5; #include "gen-icount.h" @@ -1837,8 +1837,8 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5); - tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0); - tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6); + tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0); + tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5); tcg_gen_shl_tl(t0, t0, t2); tcg_gen_subfi_tl(cpu_tmp5, 32, t2); @@ -7671,7 +7671,6 @@ static inline void gen_intermediate_code_internal(CPUState *env, cpu_tmp3_i32 = tcg_temp_new_i32(); cpu_tmp4 = tcg_temp_new(); cpu_tmp5 = tcg_temp_new(); - cpu_tmp6 = tcg_temp_new(); cpu_ptr0 = tcg_temp_new_ptr(); cpu_ptr1 = tcg_temp_new_ptr(); |