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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-04-01 10:09:29 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-23 15:04:57 -0700 |
| commit | bf8dc33bbca3d84251d40bd81fa1d832b3171ffa (patch) | |
| tree | 0417344a1c392193e2201bcfa669d28766702ff2 | |
| parent | 853f9378a325dbeec78afe3478dea277be369a3e (diff) | |
| download | focaccia-qemu-bf8dc33bbca3d84251d40bd81fa1d832b3171ffa.tar.gz focaccia-qemu-bf8dc33bbca3d84251d40bd81fa1d832b3171ffa.zip | |
target/riscv: Restrict SoftMMU mmu_index() to TCG
Move riscv_cpu_mmu_index() to the TCG-specific file, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250401080938.32278-17-philmd@linaro.org>
| -rw-r--r-- | target/riscv/cpu.c | 6 | ||||
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09ded6829a..430b02d2a5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1021,11 +1021,6 @@ bool riscv_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ -static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) -{ - return riscv_env_mmu_index(cpu_env(cs), ifetch); -} - static void riscv_cpu_reset_hold(Object *obj, ResetType type) { #ifndef CONFIG_USER_ONLY @@ -3049,7 +3044,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = riscv_cpu_class_by_name; - cc->mmu_index = riscv_cpu_mmu_index; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->get_pc = riscv_cpu_get_pc; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5aef9eef36..bee7dfd803 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -91,6 +91,11 @@ static const char *cpu_priv_ver_to_str(int priv_ver) return priv_spec_str; } +static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch) +{ + return riscv_env_mmu_index(cpu_env(cs), ifetch); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -138,6 +143,7 @@ static const TCGCPUOps riscv_tcg_ops = { .translate_code = riscv_translate_code, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, + .mmu_index = riscv_cpu_mmu_index, #ifndef CONFIG_USER_ONLY .tlb_fill = riscv_cpu_tlb_fill, |