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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:55 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:37 +0000 |
| commit | c20281b2a5048a220e09e98e002e6d3119f8c00b (patch) | |
| tree | 518ba39cc62d10589f4cedaaf191d0d45220e088 | |
| parent | 3974ff93a7632739189ed6fce374cd9c16b525fc (diff) | |
| download | focaccia-qemu-c20281b2a5048a220e09e98e002e6d3119f8c00b.tar.gz focaccia-qemu-c20281b2a5048a220e09e98e002e6d3119f8c00b.zip | |
target/arm: Advertise all page sizes for -cpu max
We support 16k pages, but do not advertize that in ID_AA64MMFR0. The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer to the same support as stage1 lookups. This setting is deprecated, so indicate support for all stage2 page sizes directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220301215958.157011-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu64.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d88662cef6..2fdc16bf18 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -796,6 +796,10 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64mmfr0; t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; |