diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2025-04-25 08:23:07 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:39:29 +1000 |
| commit | c26c4afd0ffde4f79216975ac34f419d0fcf6795 (patch) | |
| tree | 529e1753f78c16acf3155867c1c496786e5ca49c | |
| parent | bfc7936f42bac551bd859b8f32fb1f24dfcfc611 (diff) | |
| download | focaccia-qemu-c26c4afd0ffde4f79216975ac34f419d0fcf6795.tar.gz focaccia-qemu-c26c4afd0ffde4f79216975ac34f419d0fcf6795.zip | |
target/riscv: Pass ra to riscv_csrrw_do128
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250425152311.804338-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/csr.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 22149bd3fc..8af0304a36 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5588,7 +5588,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, Int128 *ret_value, Int128 new_value, - Int128 write_mask) + Int128 write_mask, uintptr_t ra) { RISCVException ret; Int128 old_value; @@ -5610,7 +5610,7 @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno, } } else if (csr_ops[csrno].write) { /* avoids having to write wrappers for all registers */ - ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value), 0); + ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value), ra); if (ret != RISCV_EXCP_NONE) { return ret; } @@ -5637,7 +5637,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, if (csr_ops[csrno].read128) { return riscv_csrrw_do128(env, csrno, ret_value, - int128_zero(), int128_zero()); + int128_zero(), int128_zero(), 0); } /* @@ -5667,7 +5667,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, } if (csr_ops[csrno].read128) { - return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask); + return riscv_csrrw_do128(env, csrno, ret_value, + new_value, write_mask, 0); } /* |