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| author | Jovanovic, Petar <petarj@mips.com> | 2012-12-11 15:06:35 +0000 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-01 11:55:57 +0100 |
| commit | c4aaba92e516ad061dff7ac2ae3c2b2b7058c404 (patch) | |
| tree | 0f6727f6757086994421d1ccddcc7562abad98e5 | |
| parent | fe65a1fad6aa140769ffda31c34a109f7d2df101 (diff) | |
| download | focaccia-qemu-c4aaba92e516ad061dff7ac2ae3c2b2b7058c404.tar.gz focaccia-qemu-c4aaba92e516ad061dff7ac2ae3c2b2b7058c404.zip | |
target-mips: Make repl_ph to sign extend to target-long
The immediate value is 9bits, should sign-extend to 16bits. The return value to register should sign-extend to target_long, as Richard says, removing an unnecessary cast works fun. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/translate.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index e81ff38476..6281e70471 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13769,9 +13769,10 @@ static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, check_dsp(ctx); { imm = (ctx->opcode >> 16) & 0x03FF; + imm = (int16_t)(imm << 6) >> 6; tcg_gen_movi_tl(cpu_gpr[ret], \ (target_long)((int32_t)imm << 16 | \ - (uint32_t)(uint16_t)imm)); + (uint16_t)imm)); } break; case OPC_REPLV_PH: |