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authorShmulik Ladkani <shmulik.ladkani@ravellosystems.com>2015-09-21 17:09:02 +0300
committerJason Wang <jasowang@redhat.com>2015-10-12 13:19:29 +0800
commitc6048f849c7e3f009786df76206e895a69de032c (patch)
treeca425fd786850c6f7dd32cdc3b674a77b4528dad
parenta7278b36fcab9af469563bd7b9dadebe2ae25e48 (diff)
downloadfocaccia-qemu-c6048f849c7e3f009786df76206e895a69de032c.tar.gz
focaccia-qemu-c6048f849c7e3f009786df76206e895a69de032c.zip
vmxnet3: Support reading IMR registers on bar0
Instead of asserting, return the actual IMR register value.
This is aligned with what's returned on ESXi.

Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
Tested-by: Dana Rubin <dana.rubin@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
-rw-r--r--hw/net/vmxnet3.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 48ced71d07..057f0dc9c0 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -1163,9 +1163,13 @@ vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
 static uint64_t
 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
 {
+    VMXNET3State *s = opaque;
+
     if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
                         VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
-        g_assert_not_reached();
+        int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
+                                         VMXNET3_REG_ALIGN);
+        return s->interrupt_states[l].is_masked;
     }
 
     VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);