diff options
| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-23 19:55:50 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-06 15:46:18 +0100 |
| commit | c90476325cf669d9bba15f4fd8d8637926f272a2 (patch) | |
| tree | 02f2b772083c11b013ffce0bc1604b631bbdcaae | |
| parent | 6eeff37b43d496deadd4cb4697f9f3f5b50d0926 (diff) | |
| download | focaccia-qemu-c90476325cf669d9bba15f4fd8d8637926f272a2.tar.gz focaccia-qemu-c90476325cf669d9bba15f4fd8d8637926f272a2.zip | |
cpus: Fix style in cpu-target.c
Fix style on code we are going to modify. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-16-philmd@linaro.org>
| -rw-r--r-- | cpu-target.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/cpu-target.c b/cpu-target.c index 83688f1d50..b925b9391e 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -48,12 +48,15 @@ static int cpu_common_post_load(void *opaque, int version_id) { CPUState *cpu = opaque; - /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the - version_id is increased. */ + /* + * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the + * version_id is increased. + */ cpu->interrupt_request &= ~0x01; tlb_flush(cpu); - /* loadvm has just updated the content of RAM, bypassing the + /* + * loadvm has just updated the content of RAM, bypassing the * usual mechanisms that ensure we flush TBs for writes to * memory we've translated code from. So we must flush all TBs, * which will now be stale. |