summary refs log tree commit diff stats
diff options
context:
space:
mode:
authorMax Chou <max.chou@sifive.com>2024-03-22 01:09:27 +0800
committerAlistair Francis <alistair.francis@wdc.com>2024-03-22 15:31:09 +1000
commitc9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603 (patch)
tree9d935afd737ae11783a8040299d1be9ad2a1693b
parent078189b327ae5c5727b51ec714d9663b1d0ca3df (diff)
downloadfocaccia-qemu-c9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603.tar.gz
focaccia-qemu-c9b07fe14d3525cd3f2fc01f46eeb3d4ed7c3603.zip
target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin
According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
the Zvfbfmin extension only requires either the V extension or the
Zve32f extension.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240321170929.1162507-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/tcg/tcg-cpu.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 63192ef54f..b5b95e052d 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -530,11 +530,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) {
-        error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension");
-        return;
-    }
-
     if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) {
         error_setg(errp, "Zvfbfmin extension depends on Zve32f extension");
         return;