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| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-22 14:55:37 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-23 00:14:05 +0200 |
| commit | cb2dbfc3516f3fc6b49c52c759b2023d5a824b52 (patch) | |
| tree | 23388916888e05fe0a230559ba1dfd50dbdcd9cb | |
| parent | 686eeb93d5738c84c59395b2ec6f8181c2b7cbed (diff) | |
| download | focaccia-qemu-cb2dbfc3516f3fc6b49c52c759b2023d5a824b52.tar.gz focaccia-qemu-cb2dbfc3516f3fc6b49c52c759b2023d5a824b52.zip | |
target-ppc: move often used CPU fields at the top of the structure
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-ppc/cpu.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 27f523f6f3..f1d7d808f0 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -579,11 +579,14 @@ struct CPUPPCState { /* floating point status and control register */ uint32_t fpscr; - CPU_COMMON + /* Next instruction pointer */ + target_ulong nip; int access_type; /* when a memory exception occurs, the access type is stored here */ + CPU_COMMON + /* MMU context - only relevant for full system emulation */ #if !defined(CONFIG_USER_ONLY) #if defined(TARGET_PPC64) @@ -663,9 +666,6 @@ struct CPUPPCState { #endif /* Those resources are used only during code translation */ - /* Next instruction pointer */ - target_ulong nip; - /* opcode handlers */ opc_handler_t *opcodes[0x40]; |