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| author | Max Filippov <jcmvbkbc@gmail.com> | 2017-02-17 16:39:30 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-01-09 09:55:39 -0800 |
| commit | d1e9b0068ac9544297042f1c4bbbf1a31a3eee3b (patch) | |
| tree | c25081aeb60c2792f98ed072f2bb325c068ce918 | |
| parent | 13f6a7cd3a736b40e14b28d7e4df45ec9333f155 (diff) | |
| download | focaccia-qemu-d1e9b0068ac9544297042f1c4bbbf1a31a3eee3b.tar.gz focaccia-qemu-d1e9b0068ac9544297042f1c4bbbf1a31a3eee3b.zip | |
target/xtensa: implement salt/saltu
SALT/SALTU are recent additions to the core Xtensa ISA that do signed/unsigned setcond. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rw-r--r-- | target/xtensa/translate.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 3e8a0015b3..bf4bd2d48d 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -2194,6 +2194,16 @@ static void translate_s32e(DisasContext *dc, const uint32_t arg[], } } +static void translate_salt(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check3(dc, arg[0], arg[1], arg[2])) { + tcg_gen_setcond_i32(par[0], + cpu_R[arg[0]], + cpu_R[arg[1]], cpu_R[arg[2]]); + } +} + static void translate_sext(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -3662,6 +3672,14 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, true}, }, { + .name = "salt", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LT}, + }, { + .name = "saltu", + .translate = translate_salt, + .par = (const uint32_t[]){TCG_COND_LTU}, + }, { .name = "sext", .translate = translate_sext, }, { |