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| author | Alistair Francis <Alistair.Francis@wdc.com> | 2019-04-20 02:27:35 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 12:09:24 -0700 |
| commit | d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c (patch) | |
| tree | 9158fedfd12c960e914eded9b45d3bc5e2e02d0c | |
| parent | 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2 (diff) | |
| download | focaccia-qemu-d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c.tar.gz focaccia-qemu-d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c.zip | |
target/riscv: Add the HSTATUS register masks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviwed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | target/riscv/cpu_bits.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 52c2169977..a179137bc1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -382,6 +382,24 @@ #define SSTATUS_SD SSTATUS64_SD #endif +/* hstatus CSR bits */ +#define HSTATUS_SPRV 0x00000001 +#define HSTATUS_STL 0x00000040 +#define HSTATUS_SPV 0x00000080 +#define HSTATUS_SP2P 0x00000100 +#define HSTATUS_SP2V 0x00000200 +#define HSTATUS_VTVM 0x00100000 +#define HSTATUS_VTSR 0x00400000 + +#define HSTATUS32_WPRI 0xFF8FF87E +#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL + +#if defined(TARGET_RISCV32) +#define HSTATUS_WPRI HSTATUS32_WPRI +#elif defined(TARGET_RISCV64) +#define HSTATUS_WPRI HSTATUS64_WPRI +#endif + /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 |