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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-18 09:25:10 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-06-09 09:21:19 -0700 |
| commit | d6084fba47bb9aef79775c1102d4b647eb58c365 (patch) | |
| tree | 1a0d7b5628e43ebc62327c7e9b2937d436d8face | |
| parent | fe079aa13d6f77f9d7323b58ab24448e73ae6a93 (diff) | |
| download | focaccia-qemu-d6084fba47bb9aef79775c1102d4b647eb58c365.tar.gz focaccia-qemu-d6084fba47bb9aef79775c1102d4b647eb58c365.zip | |
target/arm: Use a non-overlapping group for misc control
The miscellaneous control instructions are mutually exclusive within the t32 decode sub-group. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/arm/t32.decode | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c63082fc9c..c21a988f97 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -312,13 +312,13 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm &cps # Miscellaneous control - { + [ CLREX 1111 0011 1011 1111 1000 1111 0010 1111 DSB 1111 0011 1011 1111 1000 1111 0100 ---- DMB 1111 0011 1011 1111 1000 1111 0101 ---- ISB 1111 0011 1011 1111 1000 1111 0110 ---- SB 1111 0011 1011 1111 1000 1111 0111 0000 - } + ] # Note that the v7m insn overlaps both the normal and banked insn. { |