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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-05-06 13:02:32 -0500 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-05-09 11:47:54 +0100 |
| commit | da3d8b13624246702f7b8b88e37ee525a2f39ad2 (patch) | |
| tree | b73b1e9864b7a6ad035b94ae4b77d971cf31b580 | |
| parent | 58e93b48aa1b9f0e6de7e57f6f68b6dda7a8198a (diff) | |
| download | focaccia-qemu-da3d8b13624246702f7b8b88e37ee525a2f39ad2.tar.gz focaccia-qemu-da3d8b13624246702f7b8b88e37ee525a2f39ad2.zip | |
target/arm: Enable SCR and HCR bits for RAS
Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 37c5e42bc0..b6faebf4a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } valid_mask &= ~SCR_NET; + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |= SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |= SCR_TLOR; } @@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } } else { valid_mask &= ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |= SCR_TERR; + } } if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |= HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |= HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |= HCR_TLOR; } |