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| author | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2020-07-03 17:15:15 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-07-14 21:49:33 +0200 |
| commit | dda97e385b2f0fa84267a497596fe79898d48123 (patch) | |
| tree | f7677e1504319c4f75a9da2f2f640b932d03213f | |
| parent | 9788e8c9b64e4cebb01c96bab2b0e4c2d4454041 (diff) | |
| download | focaccia-qemu-dda97e385b2f0fa84267a497596fe79898d48123.tar.gz focaccia-qemu-dda97e385b2f0fa84267a497596fe79898d48123.zip | |
target/mips: Fix ADD.S FPU instruction
After merging latest QEMU upstream into our CHERI fork,
I noticed that some of the FPU tests in our MIPS baremetal
testsuite [*] started failing.
It turns out commit 1ace099f2a accidentally changed add.s
into a subtract.
[*] https://github.com/CTSRD-CHERI/cheritest
Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>")
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
| -rw-r--r-- | target/mips/fpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 7a3a61cab3..56beda49d8 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1221,7 +1221,7 @@ uint32_t helper_float_add_s(CPUMIPSState *env, { uint32_t wt2; - wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status); + wt2 = float32_add(fst0, fst1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return wt2; } |