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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-18 10:19:27 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-03-13 23:42:52 +0100 |
| commit | de5af7c5e64addc0eb89cde3cc6b0ece0225a73e (patch) | |
| tree | 4424951d86ec5f8ea788ebd84c17fcb3423f38aa | |
| parent | 965eb74bb597d4f43dbefa85244891d67634a818 (diff) | |
| download | focaccia-qemu-de5af7c5e64addc0eb89cde3cc6b0ece0225a73e.tar.gz focaccia-qemu-de5af7c5e64addc0eb89cde3cc6b0ece0225a73e.zip | |
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
We already have a macro and definition to extract / check the Special2 MUL opcode. Use it instead of the unnecessary OPC__MXU_MUL macro. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
| -rw-r--r-- | target/mips/translate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 8ab0a96a34..ad09321de8 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1464,7 +1464,6 @@ enum { */ enum { - OPC__MXU_MUL = 0x02, OPC_MXU__POOL00 = 0x03, OPC_MXU_D16MUL = 0x08, OPC_MXU_D16MAC = 0x0A, @@ -25784,7 +25783,7 @@ static void decode_opc_mxu(DisasContext *ctx, uint32_t insn) { uint32_t opcode = extract32(insn, 0, 6); - if (opcode == OPC__MXU_MUL) { + if (MASK_SPECIAL2(insn) == OPC_MUL) { uint32_t rs, rt, rd, op1; rs = extract32(insn, 21, 5); |