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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-12-18 09:53:34 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
| commit | dfa3c4c57e15912962b7d51c9b4099f46af41991 (patch) | |
| tree | 4ef6633895bae975285af7a7254a3bc68e48d8e2 | |
| parent | af651969eb23ecf018bcaa8e0761b58425de550c (diff) | |
| download | focaccia-qemu-dfa3c4c57e15912962b7d51c9b4099f46af41991.tar.gz focaccia-qemu-dfa3c4c57e15912962b7d51c9b4099f46af41991.zip | |
target/riscv: add rva22s64 cpu
Add a new profile CPU 'rva22s64' to work as an alias of -cpu rv64i,rva22s64 Like the existing rva22u64 CPU already does with the RVA22U64 profile. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218125334.37184-27-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target/riscv/cpu.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 12fe78fc52..9219c2fcc3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -36,6 +36,7 @@ #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i") #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64") +#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a8f4081922..b32681f7f3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1623,6 +1623,13 @@ static void rva22u64_profile_cpu_init(Object *obj) RVA22U64.enabled = true; } + +static void rva22s64_profile_cpu_init(Object *obj) +{ + rv64i_bare_cpu_init(obj); + + RVA22S64.enabled = true; +} #endif static const gchar *riscv_gdb_arch_name(CPUState *cs) @@ -1938,6 +1945,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), #endif }; |