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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-04-30 16:12:00 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-04-30 16:12:00 +0100 |
| commit | e0eff721e186d48dc4890414cfe117a61c103804 (patch) | |
| tree | 5d968bbfd809d5a5296a5b9731bcd1bc9a39f3cc | |
| parent | c2c768500f17fc8cdcfa44d169f089953bb22748 (diff) | |
| parent | fce6a8eceb07e27f0cdea87427f4e560dfa0b1c8 (diff) | |
| download | focaccia-qemu-e0eff721e186d48dc4890414cfe117a61c103804.tar.gz focaccia-qemu-e0eff721e186d48dc4890414cfe117a61c103804.zip | |
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream' into staging
edgar/xilinx-next-2018-01.for-upstream # gpg: Signature made Mon 30 Apr 2018 15:52:35 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-04-30.for-upstream: target-microblaze: mmu: Make the TLBX MISS bit read-only target-microblaze: mmu: Make TLBSX write-only target-microblaze: Don't clobber the IMM reg for ld/st reversed target-microblaze: Fix trap checks for FPU insns target-microblaze: Respect MSR.PVR as read-only Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/microblaze/mmu.c | 9 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 6 |
2 files changed, 10 insertions, 5 deletions
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index a0f06758f8..9d5e6aa8a5 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -182,7 +182,7 @@ done: uint32_t mmu_read(CPUMBState *env, uint32_t rn) { unsigned int i; - uint32_t r; + uint32_t r = 0; if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) { qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n"); @@ -211,6 +211,9 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) } r = env->mmu.regs[rn]; break; + case MMU_R_TLBSX: + qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n"); + break; default: r = env->mmu.regs[rn]; break; @@ -270,6 +273,10 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) env->mmu.regs[rn] = v; } break; + case MMU_R_TLBX: + /* Bit 31 is read-only. */ + env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v); + break; case MMU_R_TLBSX: { struct microblaze_mmu_lookup lu; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7628b0e25b..100883e2cc 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -424,7 +424,7 @@ static inline void msr_write(DisasContext *dc, TCGv v) /* PVR bit is not writable. */ tcg_gen_andi_tl(t, v, ~MSR_PVR); tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); - tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); + tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); tcg_temp_free(t); } @@ -952,7 +952,6 @@ static void dec_load(DisasContext *dc) tcg_gen_sub_tl(low, tcg_const_tl(3), low); tcg_gen_andi_tl(t, t, ~3); tcg_gen_or_tl(t, t, low); - tcg_gen_mov_tl(env_imm, t); tcg_temp_free(low); break; } @@ -1104,7 +1103,6 @@ static void dec_store(DisasContext *dc) tcg_gen_sub_tl(low, tcg_const_tl(3), low); tcg_gen_andi_tl(t, t, ~3); tcg_gen_or_tl(t, t, low); - tcg_gen_mov_tl(env_imm, t); tcg_temp_free(low); break; } @@ -1412,7 +1410,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && (dc->cpu->cfg.use_fpu != 1)) { + && !dc->cpu->cfg.use_fpu) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; |