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| author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2021-09-11 16:00:02 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-10-07 08:32:39 +1000 |
| commit | e47fb6c1e96a4e50603c13b8408e0745a09cd867 (patch) | |
| tree | 1d5d5a80cf285f0414bfbdcb8815213af9f8c882 | |
| parent | c5b4ee5bb799685e1c5a4a30ab40013a984daded (diff) | |
| download | focaccia-qemu-e47fb6c1e96a4e50603c13b8408e0745a09cd867.tar.gz focaccia-qemu-e47fb6c1e96a4e50603c13b8408e0745a09cd867.zip | |
target/riscv: fix clzw implementation to operate on arg1
The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index c0a6e25826..6c85c89f6d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3) static void gen_clzw(TCGv ret, TCGv arg1) { - tcg_gen_clzi_tl(ret, ret, 64); + tcg_gen_clzi_tl(ret, arg1, 64); tcg_gen_subi_tl(ret, ret, 32); } |