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| author | Jinjie Ruan <ruanjinjie@huawei.com> | 2024-04-19 14:33:01 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-25 10:21:05 +0100 |
| commit | e4eb290571606c5e6dc7739547b5056389cd92fb (patch) | |
| tree | ad04e8c0fe42b2fe0e7d157897a592a1da77d797 | |
| parent | 34d94b7af9f1dc4cae550ecc7b825c9567741a12 (diff) | |
| download | focaccia-qemu-e4eb290571606c5e6dc7739547b5056389cd92fb.tar.gz focaccia-qemu-e4eb290571606c5e6dc7739547b5056389cd92fb.zip | |
target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) come from the hcrx_el2.HCRX_VFNMI bit. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 5ff9e44649..6b224826fb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11653,10 +11653,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) break; case EXCP_IRQ: case EXCP_VIRQ: + case EXCP_NMI: + case EXCP_VINMI: addr += 0x80; break; case EXCP_FIQ: case EXCP_VFIQ: + case EXCP_VFNMI: addr += 0x100; break; case EXCP_VSERR: |