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| author | Zenghui Yu <zenghui.yu@linux.dev> | 2025-07-15 00:01:39 +0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-07-21 11:20:13 +0100 |
| commit | e6da704b711d5d731e4d933ad56cbbc25ee0a825 (patch) | |
| tree | 49f1c589fc3d566c9502e50c513cc8b27bb198fe | |
| parent | f19310b23a00b5c19f930e4d57fc298744d11740 (diff) | |
| download | focaccia-qemu-e6da704b711d5d731e4d933ad56cbbc25ee0a825.tar.gz focaccia-qemu-e6da704b711d5d731e4d933ad56cbbc25ee0a825.zip | |
hvf: arm: Emulate ICC_RPR_EL1 accesses properly
Commit a2260983c655 ("hvf: arm: Add support for GICv3") added GICv3 support
by implementing emulation for a few system registers. ICC_RPR_EL1 was
defined but not plugged in the sysreg handlers (for no good reason).
Fix it.
Fixes: a2260983c655 ("hvf: arm: Add support for GICv3")
Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250714160139.10404-3-zenghui.yu@linux.dev
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/hvf/hvf.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 861657df96..bd6b5d11de 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1361,6 +1361,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val) case SYSREG_ICC_IGRPEN0_EL1: case SYSREG_ICC_IGRPEN1_EL1: case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_RPR_EL1: case SYSREG_ICC_SGI0R_EL1: case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: @@ -1678,6 +1679,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) case SYSREG_ICC_IGRPEN0_EL1: case SYSREG_ICC_IGRPEN1_EL1: case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_RPR_EL1: case SYSREG_ICC_SGI0R_EL1: case SYSREG_ICC_SGI1R_EL1: case SYSREG_ICC_SRE_EL1: |