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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-01-10 15:01:43 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-02-18 08:29:03 -0800 |
| commit | e726f65867087d86436de05e9f372a86ec1381a6 (patch) | |
| tree | f24820f9dd1de183398fb7600c10b7641aa594a5 | |
| parent | 175aa36668d6e91157d5e5b092b441f96f46b05e (diff) | |
| download | focaccia-qemu-e726f65867087d86436de05e9f372a86ec1381a6.tar.gz focaccia-qemu-e726f65867087d86436de05e9f372a86ec1381a6.zip | |
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
These defines never should have been added as they were
never used. Only 32-bit hosts may have these opcodes and
they have them unconditionally.
Fixes: 6cb14e4de29 ("tcg/loongarch64: Add the tcg-target.h file")
Fixes: fb1f70f3685 ("tcg/riscv: Add the tcg-target.h file")
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/loongarch64/tcg-target-has.h | 2 | ||||
| -rw-r--r-- | tcg/riscv/tcg-target-has.h | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/tcg/loongarch64/tcg-target-has.h b/tcg/loongarch64/tcg-target-has.h index ac88522eef..188b00799f 100644 --- a/tcg/loongarch64/tcg-target-has.h +++ b/tcg/loongarch64/tcg-target-has.h @@ -37,8 +37,6 @@ #define TCG_TARGET_HAS_clz_i32 1 #define TCG_TARGET_HAS_ctz_i32 1 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_brcond2 0 -#define TCG_TARGET_HAS_setcond2 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 /* 64-bit operations */ diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index f35f9b31f5..98081084f2 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -37,8 +37,6 @@ #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) -#define TCG_TARGET_HAS_brcond2 1 -#define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_negsetcond_i64 1 |