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| author | Richard Henderson <rth@twiddle.net> | 2012-10-29 15:50:20 +1100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-10-30 18:52:04 +0000 |
| commit | e7d51b3450893dfcef4af4238c48baf2d4b0ed31 (patch) | |
| tree | 73a629196d428f0ffdc83094d83ab8ac2d6a1939 | |
| parent | 742a40229d991d5a1a67baba59f6b1ee85dd41f0 (diff) | |
| download | focaccia-qemu-e7d51b3450893dfcef4af4238c48baf2d4b0ed31.tar.gz focaccia-qemu-e7d51b3450893dfcef4af4238c48baf2d4b0ed31.zip | |
target-sparc: Revert setting cpu_dst to gen_dest_gpr
There is some read-after-write error within the OP=2 insns which prevents setting cpu_dst to the real output register. Until this is found and fixed, always write to a temporary first. Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| -rw-r--r-- | target-sparc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 4321393688..9e46f1424b 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2633,7 +2633,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); - TCGv cpu_dst = gen_dest_gpr(dc, rd); + TCGv cpu_dst = get_temp_tl(dc); TCGv cpu_tmp0; if (xop == 0x3a) { /* generate trap */ |