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| author | Klaus Jensen <k.jensen@samsung.com> | 2024-11-11 12:15:10 +0100 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2024-12-03 07:28:27 +0100 |
| commit | e85987786d248dd2792944e703ed4d31edbfbc54 (patch) | |
| tree | 0dbb215bddcf7d78a5b48c35a6d2bdf58f474f4e | |
| parent | 149f6e90b5b5689a4089a3432d83247d9f659684 (diff) | |
| download | focaccia-qemu-e85987786d248dd2792944e703ed4d31edbfbc54.tar.gz focaccia-qemu-e85987786d248dd2792944e703ed4d31edbfbc54.zip | |
hw/nvme: SR-IOV VFs must hardwire pci interrupt pin register to zero
The PCI Interrupt Pin Register does not apply to VFs and MUST be
hardwired to zero.
Fixes: 44c2c09488db ("hw/nvme: Add support for SR-IOV")
Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
| -rw-r--r-- | hw/nvme/ctrl.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index a38f460a78..61c114c66d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -656,6 +656,12 @@ static void nvme_irq_check(NvmeCtrl *n) if (msix_enabled(pci)) { return; } + + /* vfs does not implement intx */ + if (pci_is_vf(pci)) { + return; + } + if (~intms & n->irq_status) { pci_irq_assert(pci); } else { @@ -8544,7 +8550,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) unsigned nr_vectors; int ret; - pci_conf[PCI_INTERRUPT_PIN] = 1; + pci_conf[PCI_INTERRUPT_PIN] = pci_is_vf(pci_dev) ? 0 : 1; pci_config_set_prog_interface(pci_conf, 0x2); if (n->params.use_intel_id) { |