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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-11-19 21:55:55 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-12-10 11:44:55 +0000 |
| commit | ede97c9d71110821738a48f88ff9f10d6bec017f (patch) | |
| tree | 66e8193cfcae9ed88e082679d3800fe410f6d2b7 | |
| parent | 6e21a013fbdf54960a079dccc90772bb622e28e8 (diff) | |
| download | focaccia-qemu-ede97c9d71110821738a48f88ff9f10d6bec017f.tar.gz focaccia-qemu-ede97c9d71110821738a48f88ff9f10d6bec017f.zip | |
target/arm: Enforce M-profile VMRS/VMSR register restrictions
For M-profile before v8.1M, the only valid register for VMSR/VMRS is the FPSCR. We have a comment that states this, but the actual logic to forbid accesses for any other register value is missing, so we would end up with A-profile style behaviour. Add the missing check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201119215617.29887-7-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/translate-vfp.c.inc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 2a67ed0f6e..e100182a32 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -622,7 +622,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) * Accesses to R15 are UNPREDICTABLE; we choose to undef. * (FPSCR -> r15 is a special case which writes to the PSR flags.) */ - if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) { + if (a->reg != ARM_VFP_FPSCR) { + return false; + } + if (a->rt == 15 && !a->l) { return false; } } |