diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-01-18 15:57:51 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-02-16 14:50:59 +0100 |
| commit | f3273ba643f2d0221492381b24bbc35fb6089a48 (patch) | |
| tree | b50f0b68f7071a957da30e609d5b17c37e7dda4f | |
| parent | 25733eada6c1d4928262e77e2ee1e9ed12de18fb (diff) | |
| download | focaccia-qemu-f3273ba643f2d0221492381b24bbc35fb6089a48.tar.gz focaccia-qemu-f3273ba643f2d0221492381b24bbc35fb6089a48.zip | |
ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()
Prepares for changing cpu_interrupt() argument to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | hw/ppc.c | 12 | ||||
| -rw-r--r-- | hw/ppc.h | 6 | ||||
| -rw-r--r-- | hw/ppc405_uc.c | 16 |
3 files changed, 19 insertions, 15 deletions
diff --git a/hw/ppc.c b/hw/ppc.c index 6053bd5652..8cfb84fa13 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -300,20 +300,20 @@ static void ppc40x_set_irq(void *opaque, int pin, int level) if (level) { LOG_IRQ("%s: reset the PowerPC system\n", __func__); - ppc40x_system_reset(env); + ppc40x_system_reset(cpu); } break; case PPC40x_INPUT_RESET_CHIP: if (level) { LOG_IRQ("%s: reset the PowerPC chip\n", __func__); - ppc40x_chip_reset(env); + ppc40x_chip_reset(cpu); } break; case PPC40x_INPUT_RESET_CORE: /* XXX: TODO: update DBSR[MRR] */ if (level) { LOG_IRQ("%s: reset the PowerPC core\n", __func__); - ppc40x_core_reset(env); + ppc40x_core_reset(cpu); } break; case PPC40x_INPUT_CINT: @@ -1011,13 +1011,13 @@ static void cpu_4xx_wdt_cb (void *opaque) /* No reset */ break; case 0x1: /* Core reset */ - ppc40x_core_reset(env); + ppc40x_core_reset(cpu); break; case 0x2: /* Chip reset */ - ppc40x_chip_reset(env); + ppc40x_chip_reset(cpu); break; case 0x3: /* System reset */ - ppc40x_system_reset(env); + ppc40x_system_reset(cpu); break; } } diff --git a/hw/ppc.h b/hw/ppc.h index ee0cd16ee5..acaf0d6580 100644 --- a/hw/ppc.h +++ b/hw/ppc.h @@ -58,9 +58,9 @@ clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp); /* Embedded PowerPC reset */ -void ppc40x_core_reset (CPUPPCState *env); -void ppc40x_chip_reset (CPUPPCState *env); -void ppc40x_system_reset (CPUPPCState *env); +void ppc40x_core_reset(PowerPCCPU *cpu); +void ppc40x_chip_reset(PowerPCCPU *cpu); +void ppc40x_system_reset(PowerPCCPU *cpu); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); extern CPUWriteMemoryFunc * const PPC_io_write[]; diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index c96d103d1c..d8cbe875bd 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -1770,8 +1770,9 @@ static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) /*****************************************************************************/ /* SPR */ -void ppc40x_core_reset (CPUPPCState *env) +void ppc40x_core_reset(PowerPCCPU *cpu) { + CPUPPCState *env = &cpu->env; target_ulong dbsr; printf("Reset PowerPC core\n"); @@ -1782,8 +1783,9 @@ void ppc40x_core_reset (CPUPPCState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_chip_reset (CPUPPCState *env) +void ppc40x_chip_reset(PowerPCCPU *cpu) { + CPUPPCState *env = &cpu->env; target_ulong dbsr; printf("Reset PowerPC chip\n"); @@ -1795,7 +1797,7 @@ void ppc40x_chip_reset (CPUPPCState *env) env->spr[SPR_40x_DBSR] = dbsr; } -void ppc40x_system_reset (CPUPPCState *env) +void ppc40x_system_reset(PowerPCCPU *cpu) { printf("Reset PowerPC system\n"); qemu_system_reset_request(); @@ -1803,21 +1805,23 @@ void ppc40x_system_reset (CPUPPCState *env) void store_40x_dbcr0 (CPUPPCState *env, uint32_t val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + switch ((val >> 28) & 0x3) { case 0x0: /* No action */ break; case 0x1: /* Core reset */ - ppc40x_core_reset(env); + ppc40x_core_reset(cpu); break; case 0x2: /* Chip reset */ - ppc40x_chip_reset(env); + ppc40x_chip_reset(cpu); break; case 0x3: /* System reset */ - ppc40x_system_reset(env); + ppc40x_system_reset(cpu); break; } } |