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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-06-20 13:05:46 +0100 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-06-27 20:12:43 +0200 |
| commit | f48a2cb21824217a61ec7be797860a0702e5325c (patch) | |
| tree | 8621074ec01b02b1648d3bd47c30a9daf92e7ae3 | |
| parent | 4f91740698ced512fdad8540eb0bd232fc70aadd (diff) | |
| download | focaccia-qemu-f48a2cb21824217a61ec7be797860a0702e5325c.tar.gz focaccia-qemu-f48a2cb21824217a61ec7be797860a0702e5325c.zip | |
target/mips: Raise a RI when given fs is n/a from CTC1
Fix to raise a Reserved Instruction exception when given fs is not available from CTC1. Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
| -rw-r--r-- | target/mips/op_helper.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9025f42366..41d3634289 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2627,6 +2627,9 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); break; default: + if (env->insn_flags & ISA_MIPS32R6) { + do_raise_exception(env, EXCP_RI, GETPC()); + } return; } restore_fp_status(env); |