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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-24 14:22:18 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-28 16:14:57 +0000 |
| commit | f67957e17cbf8fc3cc5d1146a2db2023404578b0 (patch) | |
| tree | b7090da0a33dc9837e75444f1b2c1a5bf2a7c397 | |
| parent | c4ff873583834c8275586914fff714e3ae65dee4 (diff) | |
| download | focaccia-qemu-f67957e17cbf8fc3cc5d1146a2db2023404578b0.tar.gz focaccia-qemu-f67957e17cbf8fc3cc5d1146a2db2023404578b0.zip | |
target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
We will shortly use these to test for VFPv2 and VFPv3 in different situations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/cpu.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e6eac0cd2..f7a90f512e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so |