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| author | Max Filippov <jcmvbkbc@gmail.com> | 2018-08-31 01:48:26 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2018-09-17 11:09:04 -0700 |
| commit | f68774ccd8174dc80208dcb3b24924c7c1c726f9 (patch) | |
| tree | f6495fb152b05393075d27eea6bc78a9a22ca90a | |
| parent | f81aa02e0d63dbc0b7ad864e48fd5e245b0021e0 (diff) | |
| download | focaccia-qemu-f68774ccd8174dc80208dcb3b24924c7c1c726f9.tar.gz focaccia-qemu-f68774ccd8174dc80208dcb3b24924c7c1c726f9.zip | |
tests/tcg/xtensa: only generate defined exception handlers
Don't generate handlers for IRQ levels that are not defined for the CPU or for window overflow/underflow exceptions for configs w/o windowed registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rw-r--r-- | tests/tcg/xtensa/vectors.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/tcg/xtensa/vectors.S b/tests/tcg/xtensa/vectors.S index 265a181239..6a9cb3cde4 100644 --- a/tests/tcg/xtensa/vectors.S +++ b/tests/tcg/xtensa/vectors.S @@ -1,3 +1,5 @@ +#include "core-isa.h" + .macro vector name .section .vector.\name @@ -20,19 +22,33 @@ handler_\name\(): .word 0 .endm +#if XCHAL_HAVE_WINDOWED vector window_overflow_4 vector window_overflow_8 vector window_overflow_12 vector window_underflow_4 vector window_underflow_8 vector window_underflow_12 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2 vector level2 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3 vector level3 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4 vector level4 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5 vector level5 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6 vector level6 +#endif +#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7 vector level7 +#endif vector kernel vector user |