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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2016-05-03 18:03:31 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-05-30 13:20:04 +1000 |
| commit | f9ef0527ff8fe257756fb3db46b557f9980cb0eb (patch) | |
| tree | c22e549d9fd60a1ddd1de23575fa3e078839b5b4 | |
| parent | 74693da98894e685c53a660ab238e5253b211216 (diff) | |
| download | focaccia-qemu-f9ef0527ff8fe257756fb3db46b557f9980cb0eb.tar.gz focaccia-qemu-f9ef0527ff8fe257756fb3db46b557f9980cb0eb.zip | |
ppc: Change 'invalid' bit mask of tlbiel and tlbie
Otherwise it will trip on the forms used in recent architecture. Ideally, we should have different handlers for different architecture levels but our current implementation of TLB flushing is dumb enough that this will do for now. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target-ppc/translate.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 690ffd2800..868ef310d5 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9946,8 +9946,10 @@ GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), #endif GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), -GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), -GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), +/* XXX Those instructions will need to be handled differently for + * different ISA versions */ +GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), +GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), #if defined(TARGET_PPC64) GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |