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| author | Max Chou <max.chou@sifive.com> | 2025-04-08 18:39:32 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:38:50 +1000 |
| commit | fbeaf35838768086b435833cb4dc5182c73ec2bc (patch) | |
| tree | 1063db6b129bede726277478520a660f0356152d | |
| parent | 629c2a8dd7506e1cb9b6b7127604641632ac453f (diff) | |
| download | focaccia-qemu-fbeaf35838768086b435833cb4dc5182c73ec2bc.tar.gz focaccia-qemu-fbeaf35838768086b435833cb4dc5182c73ec2bc.zip | |
target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20250408103938.3623486-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: qemu-stable@nongnu.org
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 04367e1bec..b1e1db04a0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -412,7 +412,8 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && require_align(vd, s->lmul) && - require_align(vs, s->lmul); + require_align(vs, s->lmul) && + vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm); } /* |