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| author | Luc MICHEL <luc.michel@git.antfield.fr> | 2018-01-25 11:45:30 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-01-25 11:45:30 +0000 |
| commit | fc05a6f22a15503b1e95be640a62e44a06c95d25 (patch) | |
| tree | 703f6b01d882bed09c436c463459ed761d804882 | |
| parent | 71aa735b0a12201c2b14a76004ee3a58ff43798c (diff) | |
| download | focaccia-qemu-fc05a6f22a15503b1e95be640a62e44a06c95d25.tar.gz focaccia-qemu-fc05a6f22a15503b1e95be640a62e44a06c95d25.zip | |
hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is 0, the non-secure BPR value is used. However, this value must be incremented by one so that it matches the secure world number of implemented priority bits (NS world has one less priority bit compared to the Secure world). Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Message-id: 20180119145756.7629-5-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: add assert, as the gicv3 code has] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/intc/arm_gic.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 713de3084f..b7989d267f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -256,7 +256,8 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq) if (gic_has_groups(s) && !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && GIC_TEST_GROUP(irq, (1 << cpu))) { - bpr = s->abpr[cpu]; + bpr = s->abpr[cpu] - 1; + assert(bpr >= 0); } else { bpr = s->bpr[cpu]; } |