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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-12-06 22:03:35 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-12-13 20:26:02 +0100
commitffa657ee70ced89168e432ace4b4b8af5a227117 (patch)
tree1701378cbf1b9cf971934a84c90009f493dcb8de
parent07741e67542d061b45628a5de60637b006ca2de5 (diff)
downloadfocaccia-qemu-ffa657ee70ced89168e432ace4b4b8af5a227117.tar.gz
focaccia-qemu-ffa657ee70ced89168e432ace4b4b8af5a227117.zip
target/mips: Extract cpu_supports*/cpu_set* translate.c
Move cpu_supports*() and cpu_set_exception_base() from
translate.c to cpu.c.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201206233949.3783184-9-f4bug@amsat.org>
-rw-r--r--target/mips/cpu.c18
-rw-r--r--target/mips/translate.c18
2 files changed, 18 insertions, 18 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 9d7edc1ca2..3024c51a21 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -315,3 +315,21 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 {
     return (env->cpu_model->insn_flags & isa_mask) != 0;
 }
+
+bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
+{
+    const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+    return (mcc->cpu_def->insn_flags & isa) != 0;
+}
+
+bool cpu_type_supports_cps_smp(const char *cpu_type)
+{
+    const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
+    return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
+}
+
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+    vp->env.exception_base = address;
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ccc82abce0..84d2d44e5d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31766,24 +31766,6 @@ void cpu_mips_realize_env(CPUMIPSState *env)
     mvp_init(env);
 }
 
-bool cpu_type_supports_cps_smp(const char *cpu_type)
-{
-    const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
-    return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
-}
-
-bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
-{
-    const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
-    return (mcc->cpu_def->insn_flags & isa) != 0;
-}
-
-void cpu_set_exception_base(int vp_index, target_ulong address)
-{
-    MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
-    vp->env.exception_base = address;
-}
-
 void cpu_state_reset(CPUMIPSState *env)
 {
     CPUState *cs = env_cpu(env);