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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-09-16 15:01:51 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-11-06 08:27:21 -0800 |
| commit | 6046f6e94d8d530ecc28176232479889abbee47e (patch) | |
| tree | 224831b0ad2b9904c03c59e644bfcdb977c7682c /accel/tcg/cputlb.c | |
| parent | 8b1b3db71a1df58a6e28956b72f143e8cf38bdf6 (diff) | |
| download | focaccia-qemu-6046f6e94d8d530ecc28176232479889abbee47e.tar.gz focaccia-qemu-6046f6e94d8d530ecc28176232479889abbee47e.zip | |
accel/tcg: Fix condition for store_atom_insert_al16
Store bytes under a mask is fundamentally a cmpxchg, not a straight store. Use HAVE_CMPXCHG128 instead of HAVE_ATOMIC128_RW. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230916220151.526140-8-richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 13986820fe..f35c5f359b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2691,7 +2691,7 @@ static uint64_t do_st16_leN(CPUState *cpu, MMULookupPageData *p, case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ - if (!HAVE_ATOMIC128_RW) { + if (!HAVE_CMPXCHG128) { cpu_loop_exit_atomic(cpu, ra); } return store_whole_le16(p->haddr, p->size, val_le); |