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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-08-10 12:04:15 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-06 08:04:26 +0100 |
| commit | 97e03465f7dac073434373428388eb6e0998ecea (patch) | |
| tree | 994547d6104588f26024ca6479d77eaf5647adad /accel/tcg/cputlb.c | |
| parent | 0c90ba16e3b51381dc82b0f54532c6609261aea0 (diff) | |
| download | focaccia-qemu-97e03465f7dac073434373428388eb6e0998ecea.tar.gz focaccia-qemu-97e03465f7dac073434373428388eb6e0998ecea.zip | |
accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
The base qemu_ram_addr_from_host function is already in softmmu/physmem.c; move the nofail version to be adjacent. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 43bd65c973..80a3eb4f1c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1283,18 +1283,6 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, prot, mmu_idx, size); } -static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) -{ - ram_addr_t ram_addr; - - ram_addr = qemu_ram_addr_from_host(ptr); - if (ram_addr == RAM_ADDR_INVALID) { - error_report("Bad ram pointer %p", ptr); - abort(); - } - return ram_addr; -} - /* * Note: tlb_fill() can trigger a resize of the TLB. This means that all of the * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must |