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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-03-01 10:41:07 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-03-05 13:22:56 +0000 |
| commit | a0ff4a879cd3198adb4213653d51a39d053ef2d6 (patch) | |
| tree | 2dbb34a34b978b0e7900f6ecae30df37953c7b4a /accel/tcg/cputlb.c | |
| parent | a1a85a9502b5d0011320fdf490c1d6bc2f8fdc79 (diff) | |
| download | focaccia-qemu-a0ff4a879cd3198adb4213653d51a39d053ef2d6.tar.gz focaccia-qemu-a0ff4a879cd3198adb4213653d51a39d053ef2d6.zip | |
accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6243bcb179..ac986cb8ea 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1145,14 +1145,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", addr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); |