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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-05-03 13:45:26 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-05-28 08:08:47 +0100 |
| commit | a4027ed7d4becb4cb67c912c75ecd4846b148829 (patch) | |
| tree | 024a1d590669f8c477c515127953eaf5718d3294 /accel/tcg/cputlb.c | |
| parent | bdf26b5d16dd2264553308aa6bbf24b4749fcc07 (diff) | |
| download | focaccia-qemu-a4027ed7d4becb4cb67c912c75ecd4846b148829.tar.gz focaccia-qemu-a4027ed7d4becb4cb67c912c75ecd4846b148829.zip | |
target: Use cpu_pointer_wrap_notreached for strict align targets
Alpha, HPPA, and SH4 always use aligned addresses, and therefore never produce accesses that cross pages. Cc: Helge Deller <deller@gmx.de> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'accel/tcg/cputlb.c')
| -rw-r--r-- | accel/tcg/cputlb.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 81ff725cbc..49ec3ee5dc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2933,3 +2933,16 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr, { return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } + +/* + * Common pointer_wrap implementations. + */ + +/* + * To be used for strict alignment targets. + * Because no accesses are unaligned, no accesses wrap either. + */ +vaddr cpu_pointer_wrap_notreached(CPUState *cs, int idx, vaddr res, vaddr base) +{ + g_assert_not_reached(); +} |