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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-24 11:07:56 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-05-24 11:07:56 +0100 |
| commit | 636011255dec55da4cac28240ffcaa2e740f1e81 (patch) | |
| tree | 0063eae91646e226b26e1a349ae628f5f7d405cc /accel/tcg/tcg-runtime-gvec.c | |
| parent | ceac83e9ba724d915353d740a11ca08670deea59 (diff) | |
| parent | 11e2bfef799024be4a08fcf6797fe0b22fb16b58 (diff) | |
| download | focaccia-qemu-636011255dec55da4cac28240ffcaa2e740f1e81.tar.gz focaccia-qemu-636011255dec55da4cac28240ffcaa2e740f1e81.zip | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190522' into staging
Misc gvec improvements # gpg: Signature made Wed 22 May 2019 23:25:48 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190522: tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store tcg/aarch64: Allow immediates for vector ORR and BIC tcg/aarch64: Build vector immediates with two insns tcg/aarch64: Use MVNI in tcg_out_dupi_vec tcg/aarch64: Split up is_fimm tcg/aarch64: Support vector bitwise select value tcg/i386: Use umin/umax in expanding unsigned compare tcg/i386: Remove expansion for missing minmax tcg/i386: Support vector comparison select value tcg: Add TCG_OPF_NOT_PRESENT if TCG_TARGET_HAS_foo is negative tcg: Expand vector minmax using cmp+cmpsel tcg: Introduce do_op3_nofail for vector expansion tcg: Add support for vector compare select tcg: Add support for vector bitwise select tcg: Fix missing checks and clears in tcg_gen_gvec_dup_mem tcg/i386: Fix dupi/dupm for avx1 and 32-bit hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'accel/tcg/tcg-runtime-gvec.c')
| -rw-r--r-- | accel/tcg/tcg-runtime-gvec.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 0f09e0ef38..3b6052fe97 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -1444,3 +1444,17 @@ void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc) } clear_high(d, oprsz, desc); } + +void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(vec64)) { + vec64 aa = *(vec64 *)(a + i); + vec64 bb = *(vec64 *)(b + i); + vec64 cc = *(vec64 *)(c + i); + *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa); + } + clear_high(d, oprsz, desc); +} |