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| author | MollyChen <xiaoou@iscas.ac.cn> | 2024-12-05 07:36:20 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-12-20 11:22:47 +1000 |
| commit | 2fc8f50eadad5dcc99bc5de1333808b9de47a097 (patch) | |
| tree | e2996843dbcbcd253286019b5f3b0a2c2e2d5b57 /bsd-user/signal.c | |
| parent | c3de19c0cc02fc19a12e70521be907416c0d2643 (diff) | |
| download | focaccia-qemu-2fc8f50eadad5dcc99bc5de1333808b9de47a097.tar.gz focaccia-qemu-2fc8f50eadad5dcc99bc5de1333808b9de47a097.zip | |
target/riscv: add support for RV64 Xiangshan Nanhu CPU
Add a CPU entry for the RV64 XiangShan NANHU CPU which supports single-core and dual-core configurations. More details can be found at https://docs.xiangshan.cc/zh-cn/latest/integration/overview Signed-off-by: MollyChen <xiaoou@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn> [ Changes by AF - Fixup code formatting ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'bsd-user/signal.c')
0 files changed, 0 insertions, 0 deletions