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authorBlue Swirl <blauwirbel@gmail.com>2012-04-14 14:56:48 +0000
committerBlue Swirl <blauwirbel@gmail.com>2012-05-01 10:45:05 +0000
commitcc5bea608df30263f8d20facfd55d8b6ce15053d (patch)
tree487fb5df88f3a2011b640ceb05b430a2dc52e3ec /cputlb.c
parent0cac1b66c88c4cd3ec1d358091486787837215a3 (diff)
downloadfocaccia-qemu-cc5bea608df30263f8d20facfd55d8b6ce15053d.tar.gz
focaccia-qemu-cc5bea608df30263f8d20facfd55d8b6ce15053d.zip
cputlb: prepare private memory API for public consumption
Fold is_ram_rom and is_ram_rom_romd() into callers.

Change is_romd() and section_addr() to take MemoryRegion
instead of MemoryRegionSection for consistency and
use memory_region_ prefix.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'cputlb.c')
-rw-r--r--cputlb.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/cputlb.c b/cputlb.c
index b7d8f07539..7f40a62223 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -260,13 +260,15 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
 #endif
 
     address = vaddr;
-    if (!is_ram_rom_romd(section)) {
+    if (!(memory_region_is_ram(section->mr) ||
+          memory_region_is_romd(section->mr))) {
         /* IO memory case (romd handled later) */
         address |= TLB_MMIO;
     }
-    if (is_ram_rom_romd(section)) {
+    if (memory_region_is_ram(section->mr) ||
+        memory_region_is_romd(section->mr)) {
         addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
-                                 + section_addr(section, paddr);
+        + memory_region_section_addr(section, paddr);
     } else {
         addend = 0;
     }
@@ -292,13 +294,13 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
     }
     if (prot & PAGE_WRITE) {
         if ((memory_region_is_ram(section->mr) && section->readonly)
-            || is_romd(section)) {
+            || memory_region_is_romd(section->mr)) {
             /* Write access calls the I/O callback.  */
             te->addr_write = address | TLB_MMIO;
         } else if (memory_region_is_ram(section->mr)
                    && !cpu_physical_memory_is_dirty(
                            section->mr->ram_addr
-                           + section_addr(section, paddr))) {
+                           + memory_region_section_addr(section, paddr))) {
             te->addr_write = address | TLB_NOTDIRTY;
         } else {
             te->addr_write = address;