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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 10:48:56 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-06-24 10:48:56 +0000 |
| commit | 4e469a438f40a53dc6217fa5c3d456861b00d80c (patch) | |
| tree | 3eb0db99ac318738016463b56250da6bdfd64d9e /device_tree.h | |
| parent | 959a255dfbe085a47e00fd21c57e87ad4c92719e (diff) | |
| parent | 960916988b9ec45bb10400d892351f360b4aac96 (diff) | |
| download | focaccia-qemu-4e469a438f40a53dc6217fa5c3d456861b00d80c.tar.gz focaccia-qemu-4e469a438f40a53dc6217fa5c3d456861b00d80c.zip | |
Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (72 commits) PPC: BookE206: Bump MAS2 to 64bit PPC: BookE: Support 32 and 64 bit wide MAS2 PPC: Extract SPR dump generation into its own function PPC: Add e5500 CPU target PPC: BookE: Make ivpr selectable by CPU type PPC: BookE: Implement EPR SPR PPC: Add support for MSR_CM PPC: Add some booke SPR defines uImage: increase the gzip load size PPC: e500: allow users to set the /compatible property via -machine dt: make setprop argument static PPC: e500: Refactor serial dt generation dt: Add global option to set phandle start offset PPC: e500: Extend address/size of / to 64bit PPC: e500: Define addresses as always 64bit PPC: e500: Use new SOC dt format PPC: e500: Use new MPIC dt format Revert "dt: temporarily disable subtree creation failure check" PPC: e500: enable manual loading of dtb blob PPC: e500: dt: use target_phys_addr_t for ramsize ...
Diffstat (limited to 'device_tree.h')
| -rw-r--r-- | device_tree.h | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/device_tree.h b/device_tree.h index 4378685b7a..2244270b2d 100644 --- a/device_tree.h +++ b/device_tree.h @@ -14,15 +14,35 @@ #ifndef __DEVICE_TREE_H__ #define __DEVICE_TREE_H__ +void *create_device_tree(int *sizep); void *load_device_tree(const char *filename_path, int *sizep); int qemu_devtree_setprop(void *fdt, const char *node_path, - const char *property, void *val_array, int size); + const char *property, const void *val_array, int size); int qemu_devtree_setprop_cell(void *fdt, const char *node_path, const char *property, uint32_t val); +int qemu_devtree_setprop_u64(void *fdt, const char *node_path, + const char *property, uint64_t val); int qemu_devtree_setprop_string(void *fdt, const char *node_path, const char *property, const char *string); +int qemu_devtree_setprop_phandle(void *fdt, const char *node_path, + const char *property, + const char *target_node_path); +uint32_t qemu_devtree_get_phandle(void *fdt, const char *path); +uint32_t qemu_devtree_alloc_phandle(void *fdt); int qemu_devtree_nop_node(void *fdt, const char *node_path); int qemu_devtree_add_subnode(void *fdt, const char *name); +#define qemu_devtree_setprop_cells(fdt, node_path, property, ...) \ + do { \ + uint32_t qdt_tmp[] = { __VA_ARGS__ }; \ + int i; \ + \ + for (i = 0; i < ARRAY_SIZE(qdt_tmp); i++) { \ + qdt_tmp[i] = cpu_to_be32(qdt_tmp[i]); \ + } \ + qemu_devtree_setprop(fdt, node_path, property, qdt_tmp, \ + sizeof(qdt_tmp)); \ + } while (0) + #endif /* __DEVICE_TREE_H__ */ |