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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:22 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-07-16 10:40:23 +0100 |
| commit | 2d5ee9e7a7dd495d233cf9613a865f63f88e3375 (patch) | |
| tree | 3cf2c0776c76a23a1fd546535b63abd5a285c24b /disas/mips.c | |
| parent | 3749c11a720689694101dcf2ebc43217a02f960f (diff) | |
| parent | 908680c6441ac468f4871d513f42be396ea0d264 (diff) | |
| download | focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.tar.gz focaccia-qemu-2d5ee9e7a7dd495d233cf9613a865f63f88e3375.zip | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150716' into staging
MIPS patches 2015-07-16 Changes: * bug fixes # gpg: Signature made Thu Jul 16 09:04:56 2015 BST using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20150716: target-mips: fix page fault address for LWL/LWR/LDL/LDR linux-user: Fix MIPS N64 trap and break instruction bug target-mips: fix resource leak reported by Coverity target-mips: fix logically dead code reported by Coverity target-mips: correct DERET instruction target-mips: fix ASID synchronisation for MIPS MT disas/mips: fix disassembling R6 instructions target-mips: fix to clear MSACSR.Cause target-mips: fix MIPS64R6-generic configuration Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'disas/mips.c')
| -rw-r--r-- | disas/mips.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/disas/mips.c b/disas/mips.c index 32940feb95..01336a8385 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1296,12 +1296,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, {"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, {"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6}, -{"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, -{"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, -{"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, -{"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, -{"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6}, -{"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6}, +{"ll", "t,+o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, +{"sc", "t,+o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6}, +{"lld", "t,+o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, +{"scd", "t,+o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6}, +{"pref", "h,+o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6}, +{"cache", "k,+o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6}, {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, {"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I32R6}, |