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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-12 13:10:30 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-07-10 22:29:14 +1000 |
| commit | 01b1361f84d55a86be486323836a29488b52e3a6 (patch) | |
| tree | e160909f6daedea3898a94fd6cc14ddc144f7af6 /disas/riscv.c | |
| parent | 5d326db2f9d0f4c90a3298f12bcb803e7bf302dc (diff) | |
| download | focaccia-qemu-01b1361f84d55a86be486323836a29488b52e3a6.tar.gz focaccia-qemu-01b1361f84d55a86be486323836a29488b52e3a6.zip | |
disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an instruction, but is a catch-all value in case we have no match in the decoder. Let's make the value a shared one, so that other compile units can reuse it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv.c')
| -rw-r--r-- | disas/riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index 4a55348267..b6ced2a26a 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -23,7 +23,7 @@ #include "disas/riscv.h" typedef enum { - rv_op_illegal = 0, + /* 0 is reserved for rv_op_illegal. */ rv_op_lui = 1, rv_op_auipc = 2, rv_op_jal = 3, |