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| author | Max Chou <max.chou@sifive.com> | 2023-10-26 23:18:19 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:06:02 +1000 |
| commit | 434c609bef445e0dd13d514c5b12f8e47a73cd1d (patch) | |
| tree | 10e5777be67f8c75e16ee8e4e6aead7431a8b4da /disas/riscv.h | |
| parent | ea363626ff65b2b8e6c590812f89546d5779612f (diff) | |
| download | focaccia-qemu-434c609bef445e0dd13d514c5b12f8e47a73cd1d.tar.gz focaccia-qemu-434c609bef445e0dd13d514c5b12f8e47a73cd1d.zip | |
disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231026151828.754279-13-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv.h')
| -rw-r--r-- | disas/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/disas/riscv.h b/disas/riscv.h index b242d73b25..19e5ed2ce6 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -152,6 +152,7 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_vror_vi, rv_codec_zcb_ext, rv_codec_zcb_mul, rv_codec_zcb_lb, |