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| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-21 16:23:01 +0200 |
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| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-21 18:09:54 +0200 |
| commit | 19a18edd8860064d3dbe71bc5315347bcfeb4c24 (patch) | |
| tree | 0ae18762c542cb761b73e2125c8fb52dc296496e /docs/devel/secure-coding-practices.rst | |
| parent | 57b9c589b621b40f3a81662ad1aa960ab6a60497 (diff) | |
| download | focaccia-qemu-19a18edd8860064d3dbe71bc5315347bcfeb4c24.tar.gz focaccia-qemu-19a18edd8860064d3dbe71bc5315347bcfeb4c24.zip | |
target/tricore: Honour privilege changes on PSW write
the CPU can change the privilege level by writing the corresponding bits in PSW. If this happens all instructions after this 'mtcr' in the TB are translated with the wrong privilege level. So we have to exit to the cpu_loop() and start translating again with the new privilege level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <20230621142302.1648383-8-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'docs/devel/secure-coding-practices.rst')
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