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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 09:02:37 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:17 +0100 |
| commit | 29f80e7d831f123268fcc15c5516b06eeec5eab5 (patch) | |
| tree | 7eb991f1aedb632e3cd213ae4a92340b96d7ebaa /docs/devel/secure-coding-practices.rst | |
| parent | 2c8cb5888e998d7ba8e36c312644a11d832dbe9c (diff) | |
| download | focaccia-qemu-29f80e7d831f123268fcc15c5516b06eeec5eab5.tar.gz focaccia-qemu-29f80e7d831f123268fcc15c5516b06eeec5eab5.zip | |
target/arm: Implement MVE FP max/min across vector
Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These calculate the maximum or minimum of floating point elements across a vector, starting with a value in a general purpose register and returning the result there. The pseudocode silences a possible SNaN in the accumulating result on every iteration (by calling FPConvertNaN), but we do it only on the input ra, because if none of the inputs to float*_maxnum or float*_minnum are SNaNs then the result can't be an SNaN. Note that we can't use the float*_maxnuma() etc functions we defined earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute value of the starting general-purpose register value, which could be negative. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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