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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-12-18 17:43:21 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:47 +1000 |
| commit | 3ca78c0689d504366d7c8dc516e7144940aa7c0c (patch) | |
| tree | 7ca2c00d2ad5684d1a6d8e944835e28a033634eb /docs/devel/secure-coding-practices.rst | |
| parent | 0d71f0a34938a6ac11953ae3dbec40113d2838a1 (diff) | |
| download | focaccia-qemu-3ca78c0689d504366d7c8dc516e7144940aa7c0c.tar.gz focaccia-qemu-3ca78c0689d504366d7c8dc516e7144940aa7c0c.zip | |
target/riscv/kvm: add RVV and Vector CSR regs
Add support for RVV and Vector CSR KVM regs vstart, vl and vtype. Support for vregs[] requires KVM side changes and an extra reg (vlenb) and will be added later. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218204321.75757-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs/devel/secure-coding-practices.rst')
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