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authorAndrew Jeffery <andrew@aj.id.au>2021-10-12 08:20:08 +0200
committerCédric Le Goater <clg@kaod.org>2021-10-12 08:20:08 +0200
commit5857974d5d1133455e3c33e7c740786722418588 (patch)
treed469eb77773f693ae09722202c217c2cc82d88fc /docs/devel/secure-coding-practices.rst
parent87bd33e8b0d2e08a6030ffced9433e5927360de5 (diff)
downloadfocaccia-qemu-5857974d5d1133455e3c33e7c740786722418588.tar.gz
focaccia-qemu-5857974d5d1133455e3c33e7c740786722418588.zip
hw/adc: Add basic Aspeed ADC model
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar to the STM ADC already in
the tree.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
[clg : support for multiple engines (AST2600) ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[pdel : refactored engine register struct fields to regs[] array field]
[pdel : added guest-error checking for upper-8 channel regs in AST2600]
[pdel : allow 16-bit reads of the channel data registers]
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20211005052604.1674891-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'docs/devel/secure-coding-practices.rst')
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