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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-15 10:05:36 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 15:17:54 -0800 |
| commit | e80865e5f36e6bb38eae551ecb09f069b9e21e93 (patch) | |
| tree | 7817d823a7690ec35787bbe6396a779148ffe337 /docs/devel/secure-coding-practices.rst | |
| parent | 2bc2853f157db43c98bf1458f9af0ed11205b3f2 (diff) | |
| download | focaccia-qemu-e80865e5f36e6bb38eae551ecb09f069b9e21e93.tar.gz focaccia-qemu-e80865e5f36e6bb38eae551ecb09f069b9e21e93.zip | |
target/riscv: Add support for Zvfh/zvfhmin extensions
Zvfh supports vector float point instructions with SEW = 16 and supports conversions between 8-bit integers and binary16 values. Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-12-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'docs/devel/secure-coding-practices.rst')
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